Metal-oxide semiconductor ("MOS") technology is now preferred in manufacturing many semiconductor devices and circuits. Complementary MOS ("CMOS") circuitry is often a preferred technology for implementing integrated circuits because of the low power dissipation in CMOS circuitry.
CMOS technology advances have been characterized by a lowering of the power supply voltage required to activate the CMOS circuitry. Various CMOS technologies require 5 volt, 3.6 volt, 2.5 volt, and 1.8 volt power supplies. Circuits produced with each of these different CMOS technologies produce a digital signal at a voltage level approximately equal to the supply voltage. Thus, for example, a 3.6 volt CMOS circuit will provide digital signals with a "high" signal level of approximately 3.6 volts while a 2.5 volt CMOS circuit will provide digital signals having a "high" level of approximately 2.5 volts.
A CMOS circuit designed for operation at one power supply voltage level generally might not accept digital signals produced by a higher voltage CMOS circuit. One reason for this incompatibility is that higher voltage CMOS signals may be too high to be safely applied to the thin metal oxide gate of the MOS devices included in the lower voltage CMOS circuit. The higher voltage input signal may damage the lower voltage CMOS circuit or cause it to malfunction.
However, certain computer system designs may utilize many CMOS chips requiring different power supply voltages. In this mixed CMOS situation, the output signals from one CMOS circuit are not directly compatible with the input signal requirements of another CMOS circuit in the system. Therefore, the signals from a higher voltage CMOS circuit in a system must be converted to a level acceptable to a second, lower voltage CMOS circuit which may require an input from the higher voltage circuit.
One prior art arrangement for converting a digital signal to a lower voltage signal comprised an N-type transistor having its source-drain conduction path connecting an input and an output. The input was connected to receive a signal at one voltage level and the output provided signals at the desired lower voltage level. The gate of the N-type device was connected to receive a supply voltage at the desired lower voltage signal level. In this single N-type device conversion arrangement, the maximum voltage at the output was limited to the saturation voltage of the device, that is, the voltage at the gate of the N-type device minus the threshold voltage of the N-type device.
In a 1.8 volt CMOS system, the "high" signal level VIH may range from 1.8 volts to 1.4 volts while the "low" signal level VIL may range from 0.4 volts to 0 volts. Where the prior art N-type conversion circuit was used to convert from a higher voltage signal level to a 1.8 volt system signal, and assuming a threshold voltage for the N-type device of 0.4 volts, the maximum voltage at the output of the N-type conversion circuit was 1.8 volts minus 0.4 volts (1.4 volts). This maximum 1.4 volt output from the prior art conversion circuit just met the VIH of the 1.8 volt system. However, with a 10% tolerance, the power supply voltage for the 1.8 volt system may fall to 1.62 volts. At this minimum power supply level, the maximum voltage output of the N-type conversion circuit equalled 1.62 volts minus 0.4 volts (1.22 volts). This maximum 1.22 volt output from the prior art conversion circuit was below the VIH of the 1.8 volt system. Thus, the prior art N-type conversion arrangement was unacceptable for use in converting to a 1.8 volt system signal. Furthermore, the threshold voltage did not scale well as the power supply and device size became smaller and smaller. That meant that the threshold voltage became a larger and larger part of the power supply in terms of percentage.